Yosys Python Packages

edalize

An abstraction library for interfacing EDA tools

yowasp-yosys

Unofficial Yosys WebAssembly packages

cxxrtl-vpi

An IEEE-1364 VPI interface for CXXRTL (the Yosys C++ simulation backend), so cocotb can drive CXXRTL models.

digsim-logic-simulator

An interactive digital logic simulator with verilog support (Yosys)

sc-cxxrtl

A CXXRTL (Yosys) cocotb simulator for SiliconCompiler — installed, not patched in

torii

A Python-based HDL and framework for silicon-based witchcraft

sphinxcontrib-hdl-diagrams

Generate diagrams from HDL in Sphinx.

sphinxcontrib-verilog-diagrams

Compatibility stub for renamed to sphinxcontrib-hdl-diagrams.

hdlconv

HDL converter, based on GHDL, Yosys, and the plugins ghdl-yosys-plugin and yosys-slang

pyfpga

A Python package to use FPGA development tools programmatically.

yowasp-boolector

boolector Satisfiability Modulo Theories (SMT) solver

crczero

CRC HDL code generator: Verilog-2001, SystemVerilog, VHDL-1993

riocore

riocore

riogui

RealtimeIO for LinuxCNC based on an FPGA