Yosys Python Packages

edalize

An abstraction library for interfacing EDA tools

yowasp-yosys

Unofficial Yosys WebAssembly packages

neosyn-fpga-mcp

MCP server for FPGA hardware design in C⏚ - agents write a C-like HDL; the server compiles, checks, generates Verilog and synth-checks against the real toolchain.

digsim-logic-simulator

An interactive digital logic simulator with verilog support (Yosys)

cg-agent-kit

MCP server for FPGA hardware design in C⏚ - agents write a C-like HDL; the server compiles, checks, generates Verilog and synth-checks against the real toolchain.

sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

torii

A Python-based HDL and framework for silicon-based witchcraft

sphinxcontrib-verilog-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

hdlconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

chipleap

From an AI workload or your own RTL to a chip GDS on IHP SG13G2, checked with DRC and LVS: architecture exploration with every decision explained, X-HEEP SoC or AXI4 IP generation, and an open digital flow from lint and formal to DFT, pad ring and signoff. MCP server.

pyfpga

A Python package to use FPGA development tools programmatically.

cxxrtl-vpi

An IEEE-1364 VPI interface for CXXRTL (the Yosys C++ simulation backend), so cocotb can drive CXXRTL models.

sc-cxxrtl

A CXXRTL cocotb simulator for SiliconCompiler — installed, not patched in. Built on cxxrtl-vpi.

yowasp-boolector

Unofficial nextpnr WebAssembly packages

crczero

Generates synthesizable VHDL & Verilog, parallel CRC modules from a built-in catalog of 80+ named algorithms, or from user-supplied polynomial parameters. Optional AXI4-S wrappers, Self-checking testbenches with VCD waveform output are included. Hardware tested.

riocore

RealtimeIO for LinuxCNC based on an FPGA

riogui

RealtimeIO for LinuxCNC based on an FPGA