Yosys Python Packages

edalize

An abstraction library for interfacing EDA tools

yowasp-yosys

Unofficial Yosys WebAssembly packages

digsim-logic-simulator

An interactive digital logic simulator with verilog support (Yosys)

torii

Torii hardware definition language

sphinxcontrib-hdl-diagrams

Generate diagrams from HDL in Sphinx.

sphinxcontrib-verilog-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

hdlconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

pyfpga

A Python package to use FPGA development tools programmatically.

crczero

Generates synthesizable VHDL & Verilog, parallel CRC modules from a built-in catalog of 80+ named algorithms, or from user-supplied polynomial parameters. Optional AXI4-S wrappers, Self-checking testbenches with VCD waveform output are included. Hardware tested.

yowasp-boolector

boolector Satisfiability Modulo Theories (SMT) solver

riocore

riocore

riogui

riogui