PyRank
  • Insights
  • PyPI
  • GitHub
  • Search
  • Compare
  • Advisories
  • Ecosystem
  • About

Yosys Python Packages

Python packages with the GitHub topic yosys. Sorted by relevance, with stars and monthly downloads.
olofk
edalize

An abstraction library for interfacing EDA tools

165K 770 226
YoWASP
yowasp-yosys

Unofficial Yosys WebAssembly packages

59K 76 2
freand76
digsim-logic-simulator

An interactive digital logic simulator with verilog support (Yosys)

771 28 0
shrine-maiden-heavy-industries
torii

Torii hardware definition language

555 39 4
SymbiFlow
sphinxcontrib-hdl-diagrams

Generate diagrams from HDL in Sphinx.

494 65 16
SymbiFlow
sphinxcontrib-verilog-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

491 65 16
PyFPGA
hdlconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

451 26 2
PyFPGA
pyfpga

A Python package to use FPGA development tools programmatically.

269 146 16
bard0-design
crczero

Generates synthesizable VHDL & Verilog, parallel CRC modules from a built-in catalog of 80+ named algorithms, or from user-supplied polynomial parameters. Optional AXI4-S wrappers, Self-checking testbenches with VCD waveform output are included. Hardware tested.

130 4 1
YoWASP
yowasp-boolector

boolector Satisfiability Modulo Theories (SMT) solver

108 2 1
multigcs
riocore

riocore

102 87 18
multigcs
riogui

riogui

79 87 18
    • Data from PyPI, GitHub, ClickHouse, and BigQuery