Vlsi Python Packages

rta-constraint-intelligence

Ṛta — deterministic SDC constraint intelligence for block-level VLSI design. Validate, generate, lint, convert and analyze timing constraints before STA, with clock intelligence, coverage, conflict detection, readiness scoring, diff, MMC and CI gates. 1,200+ tests, 119 rules, fully offline — no LLM.

physdes-py

🧱 Physical Design Python Code

eda-netlist-parser

A pure-Python parser for SPICE, Spectre, CDL, and DSPF netlist files — extracts subcircuit, port, device, and parasitic data for EDA automation and library characterization workflows.

pydesignflow

Micro-Framework for FPGA / VLSI Design Flow in Python

rawast

Universal bidirectional grammar-driven engine for EDA file formats. One grammar drives parse + save for GDSII, LEF, DEF, Tcl.

dreamplace

Deep learning toolkit-enabled VLSI placement

eda-sdf-parser

A pure-Python parser for Standard Delay Format (SDF) files used in EDA timing flows.

hammer-irview

Intermediate Representation Viewer for the UC Berkeley HAMMER VLSI Framework