Vhdl Python Packages

cocotb

cocotb: Python-based chip (RTL) verification

edalize

An abstraction library for interfacing EDA tools

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

siliconcompiler

Modular hardware build system

vsg

Style guide enforcement for VHDL

pyvhdlmodel

An abstract language model of VHDL written in Python.

vunit-hdl

VUnit is a unit testing framework for VHDL/SystemVerilog

fabulous-bit-gen

Bitstream generation for FABulous FPGAs

tsfpga

A flexible and scalable development platform for modern FPGA projects.

hdl-registers

An open-source HDL register code generator fast enough to run in real time.

axion-hdl

Axion-HDL: Automated AXI Register Space Generation Tool

hdlconvertorast

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

tree-sitter-vhdl

A VHDL parser for syntax highlighting.

pyxhdl

Python Frontend For VHDL And Verilog

pyvhdlparser

Streaming based VHDL parser.

simonspeckciphers

Implementations of the Simon and Speck Block Ciphers

pyedaa-projectmodel

An abstract model of EDA tool projects.

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

simplhdl

A framework for simulating and implementing HDL designs

hwtlib

hardware library for hwt (= ipcore repo)

monogate-forge

EML language and compiler for verified mathematical computation. 33 backends (software · GPU shaders · FPGA · Lean proofs · safety-critical) from one source, with chain-order analysis and Lean-checkable contracts on every function.

fabulous-fpga

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

pyversioning

Write version information collected from (CI) environment for any programming language as source file.