Vhdl Python Packages

cocotb

cocotb: Python-based chip (RTL) verification

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

edalize

An abstraction library for interfacing EDA tools

siliconcompiler

Modular hardware build system

vsg

Style guide enforcement for VHDL

vunit-hdl

VUnit is a unit testing framework for VHDL/SystemVerilog

pyvhdlmodel

An abstract language model of VHDL written in Python.

hdl-ip-packager

A package manager and dependency resolver for HDL IP cores

fabulous-bit-gen

Bitstream generation for FABulous FPGAs

tree-sitter-vhdl

A VHDL parser for syntax highlighting.

tsfpga

A flexible and scalable development platform for modern FPGA projects.

simplhdl

Simulation and implementation flow for hardware description languages

simonspeckciphers

Implementations of the Simon and Speck Block Ciphers

hdlconvertorast

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

pyvhdlparser

Streaming based VHDL parser.

axion-hdl

Axion-HDL: Automated AXI Register Space Generation Tool

hdl-registers

An open-source HDL register code generator fast enough to run in real time.

pyedaa-projectmodel

An abstract model of EDA tool projects.

hdlpkg

A package manager and dependency resolver for HDL IP cores

hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

pyversioning

Gather version information and export as any programming language source file for inclusion into compilation.

fabulous-fpga

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️