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Verilog Python Packages

Python packages with the GitHub topic verilog. Sorted by relevance, with stars and monthly downloads.
tree-sitter
tree-sitter-verilog

SystemVerilog grammar for tree-sitter

542K 114 41
cocotb
cocotb

cocotb: Python-based chip (RTL) verification

315K 2K 640
SystemRDL
peakrdl

Control and status register code generator toolchain

272K 195 41
MikePopoloski
pyslang

SystemVerilog compiler and language services

231K 1K 224
olofk
edalize

An abstraction library for interfacing EDA tools

165K 770 226
olofk
fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

151K 1K 271
cocotb
cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

130K 78 49
cirosantilli
vcdvcd

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

103K 69 26
siliconcompiler
siliconcompiler

Modular hardware build system

80K 1K 128
SystemRDL
peakrdl-cli

Control and status register code generator toolchain

63K 195 41
najaeda
najaeda

Structural Netlist API (and more) for EDA post synthesis flow development

31K 137 23
marcelwa
aigverse

A Python library for working with logic networks, synthesis, and optimization.

23K 79 5
fpgawars
apio

:seedling: Open source ecosystem for open FPGA boards

21K 980 155
FPGA-Research
fabulous-bit-gen

Bitstream generation for FABulous FPGAs

7K 2 3
tsfpga
tsfpga

A flexible and scalable development platform for modern FPGA projects.

6K 43 8
Nic30
hdlconvertorast

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

2K 41 12
dau-dev
verilator

Python/PyPI wrapper for Verilator

2K 7 1
davidel
pyxhdl

Python Frontend For VHDL And Verilog

2K 27 2
cristian-mattarei
cosa

CoreIR Symbolic Analyzer

2K 75 18
mtdsousa
antlr4-verilog

Generated files from ANTLR4 for Verilog parsing in Python

1K 12 0
pymtl
pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

1K 453 57
sgherbst
svinst

Determines the modules declared and instantiated in a SystemVerilog file

1K 51 6
edaa-org
pyedaa-projectmodel

An abstract model of EDA tool projects.

1K 14 1
Nic30
hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

1K 225 30
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