Verilog Python Packages

tree-sitter-verilog

SystemVerilog grammar for tree-sitter

pyslang

SystemVerilog compiler and language services

cocotb

cocotb: Python-based chip (RTL) verification

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

peakrdl

Control and status register code generator toolchain

siliconcompiler

Modular hardware build system

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

edalize

An abstraction library for interfacing EDA tools

peakrdl-cli

Control and status register code generator toolchain

vcdvcd

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

najaeda

Netlist API (and more) for EDA flow development

apio

:seedling: Open source ecosystem for open FPGA boards

aigverse

A Python library for working with logic networks, synthesis, and optimization.

verilator

Python/PyPI wrapper for Verilator

hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

verible

Python/PyPI wrapper for Verible

astli

SystemVerilog language tooling, written in Rust

xeda

Cross EDA Abstraction and Automation

neosyn-fpga-mcp

MCP server for FPGA hardware design in C⏚ - agents write a C-like HDL; the server compiles, checks, generates Verilog and synth-checks against the real toolchain.

holoso

Verilog synthesis directly from idiomatic Python for numerical/DSP-heavy applications. Not an HDL.

py4hw

Hardware Design/Visualization/Simulation/RTLGeneration Framework

naja-scope

MCP server for AI agents to explore SystemVerilog/Verilog netlists: trace connectivity, walk hierarchy, jump to source - without pasting RTL into context. Built on najaeda.

zkf

Zubax Kulibin Float (ZKF) -- an efficient floating-point engine for controls & embedded following IEEE 754 sans NaN and subnormals

tsfpga

A flexible and scalable development platform for modern FPGA projects.