Verilog Python Packages

tree-sitter-verilog

SystemVerilog grammar for tree-sitter

cocotb

cocotb: Python-based chip (RTL) verification

pyslang

SystemVerilog compiler and language services

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

peakrdl

Control and status register code generator toolchain

edalize

An abstraction library for interfacing EDA tools

vcdvcd

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

peakrdl-cli

Control and status register code generator toolchain

siliconcompiler

Modular hardware build system

najaeda

Netlist API (and more) for EDA flow development

apio

:seedling: Open source ecosystem for open FPGA boards

aigverse

A Python library for working with logic networks, synthesis, and optimization.

sc-neurocore

Universal Stochastic Computing Framework for Neuromorphic Hardware — Rust SIMD engine, Python simulation, Verilog RTL, HDC/VSA, SCPN integration

fabulous-bit-gen

Bitstream generation for FABulous FPGAs

tsfpga

A flexible and scalable development platform for modern FPGA projects.

simplhdl

Simulation and implementation flow for hardware description languages

hdlconvertorast

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

verilator

Python/PyPI wrapper for Verilator

holoso

Simple high-level synthesis of portable Verilog directly from idiomatic imperative Python for numerical/DSP-heavy applications. Not an HDL.

pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

pyedaa-projectmodel

An abstract model of EDA tool projects.

hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

cosa

CoreIR Symbolic Analyzer