Verilog Python Packages

tree-sitter-verilog

SystemVerilog grammar for tree-sitter

cocotb

cocotb: Python-based chip (RTL) verification

peakrdl

Control and status register code generator toolchain

pyslang

SystemVerilog compiler and language services

edalize

An abstraction library for interfacing EDA tools

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

vcdvcd

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

siliconcompiler

Modular hardware build system

peakrdl-cli

Control and status register code generator toolchain

najaeda

Structural Netlist API (and more) for EDA post synthesis flow development

aigverse

A Python library for working with logic networks, synthesis, and optimization.

apio

:seedling: Open source ecosystem for open FPGA boards

fabulous-bit-gen

Bitstream generation for FABulous FPGAs

tsfpga

A flexible and scalable development platform for modern FPGA projects.

hdlconvertorast

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

verilator

Python/PyPI wrapper for Verilator

pyxhdl

Python Frontend For VHDL And Verilog

cosa

CoreIR Symbolic Analyzer

antlr4-verilog

Generated files from ANTLR4 for Verilog parsing in Python

pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

svinst

Determines the modules declared and instantiated in a SystemVerilog file

pyedaa-projectmodel

An abstract model of EDA tool projects.

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++