Verilator Python Packages

edalize

An abstraction library for interfacing EDA tools

verilator

Python/PyPI wrapper for Verilator

dau-build

Build tools for dau projects

svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

dau-sim

Cycle-accurate hardware simulator

chipleap

From an AI workload or your own RTL to a chip GDS on IHP SG13G2, checked with DRC and LVS: architecture exploration with every decision explained, X-HEEP SoC or AXI4 IP generation, and an open digital flow from lint and formal to DFT, pad ring and signoff. MCP server.

svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

erroranalyzer

Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

playhdl

🪀 Tool to play with HDL (inspired by EdaPlayground)

smgp

Persistent, hallucination-free AI reasoning through spectral graph theory, hyperdimensional computing, and dedicated hardware acceleration.