verilator
An abstraction library for interfacing EDA tools
Python/PyPI wrapper for Verilator
Library for working with fixed-point numbers in SystemVerilog
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
Persistent, hallucination-free AI reasoning through spectral graph theory, hyperdimensional computing, and dedicated hardware acceleration.
🪀 Tool to play with HDL (inspired by EdaPlayground)
