Uvm Python Packages

cocotb

cocotb: Python-based chip (RTL) verification

peakrdl

Control and status register code generator toolchain

peakrdl-uvm

Generate UVM register model from compiled SystemRDL input

peakrdl-cli

Control and status register code generator toolchain

ailoy-py

AI agent builder with a VM at its heart. Every agent gets its own microVM sandbox to install software, run code and use the GPU in. Python, Node.js and Rust.

virtx

Disposable Linux VMs for your own code. Runs microVMs on Linux, macOS and Windows hosts with no Docker or daemon, GPU through Vulkan, and host folders mounted in. Python, Node.js and Rust.

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

traceweave-mcp

Open-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM source, hierarchy, and connectivity to trace failures to root cause.

uvmgen

uvm framework generator

erroranalyzer

Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

ralbot-uvm

Generate UVM register model from compiled SystemRDL input

pyralgen

A lightweight Python-based code generator to produce RAL UVM with coverage