Timing Analysis Python Packages

openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

rta-constraint-intelligence

Ṛta — deterministic SDC constraint intelligence for block-level VLSI design. Validate, generate, lint, convert and analyze timing constraints before STA, with clock intelligence, coverage, conflict detection, readiness scoring, diff, MMC and CI gates. 1,200+ tests, 119 rules, fully offline — no LLM.

pytorch-benchmark

Easily benchmark PyTorch model FLOPs, latency, throughput, allocated gpu memory and energy consumption

eda-liberty-parser

A pure-Python parser for Liberty (.lib) files — extracts cell timing, power, and pin data from standard-cell and pad libraries for EDA automation workflows.

eda-sdf-parser

A pure-Python parser for Standard Delay Format (SDF) files used in EDA timing flows.