Systemverilog Python Packages

pyslang

SystemVerilog compiler and language services

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl

Control and status register code generator toolchain

edalize

An abstraction library for interfacing EDA tools

peakrdl-cli

Control and status register code generator toolchain

verilator

Python/PyPI wrapper for Verilator

hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

verible

Python/PyPI wrapper for Verible

astli

SystemVerilog language tooling, written in Rust

naja-scope

MCP server for AI agents to explore SystemVerilog/Verilog netlists: trace connectivity, walk hierarchy, jump to source - without pasting RTL into context. Built on najaeda.

tsfpga

A flexible and scalable development platform for modern FPGA projects.

booley-rtl

The open-source agentic RTL IDE

pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

simplhdl

Simulation and implementation flow for hardware description languages

hdl-checker

Repurposing existing HDL tools to help writing better code

antlr4-verilog

Generated files from ANTLR4 for Verilog parsing in Python

svinst

Determines the modules declared and instantiated in a SystemVerilog file

cosa

CoreIR Symbolic Analyzer

genesispy

Python port of Genesis2 (https://github.com/StanfordVLSI/Genesis2)

hdlconvertorast

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

floogen

A Fast, Low-Overhead On-chip Network

dau-build

Build tools for dau projects

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++