Systemverilog Python Packages

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl

Control and status register code generator toolchain

pyslang

SystemVerilog compiler and language services

edalize

An abstraction library for interfacing EDA tools

peakrdl-cli

Control and status register code generator toolchain

tsfpga

A flexible and scalable development platform for modern FPGA projects.

hdlconvertorast

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

verilator

Python/PyPI wrapper for Verilator

socx-cli

Unified command-line tool for EDA development teams to streamline common tasks and tools, and unify them under a single configurable CLI menu to increase accessibility and transparency of tools and scripts in collaborative development environments.

pyxhdl

Python Frontend For VHDL And Verilog

cosa

CoreIR Symbolic Analyzer

antlr4-verilog

Generated files from ANTLR4 for Verilog parsing in Python

pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

svinst

Determines the modules declared and instantiated in a SystemVerilog file

simplhdl

A framework for simulating and implementing HDL designs

svmodule

SystemVerilog & Verilog Module I/O parser and printer

sv-trace

SystemVerilog static analysis library for RTL tracing, verification, and code quality

hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

sphinx-verilog-domain

Verilog Domain for Sphinx

sv2svg

SystemVerilog (.sv) to SVG visualizer using Schemdraw logic gates.

ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

pyslang-dev

SystemVerilog compiler and language services

svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats