Systemverilog Python Packages

pyslang

SystemVerilog compiler and language services

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl

Control and status register code generator toolchain

edalize

An abstraction library for interfacing EDA tools

peakrdl-cli

Control and status register code generator toolchain

hdl-ip-packager

A package manager and dependency resolver for HDL IP cores

tsfpga

A flexible and scalable development platform for modern FPGA projects.

simplhdl

Simulation and implementation flow for hardware description languages

hdlconvertorast

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

verilator

Python/PyPI wrapper for Verilator

pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

hdlpkg

A package manager and dependency resolver for HDL IP cores

hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

cosa

CoreIR Symbolic Analyzer

antlr4-verilog

Generated files from ANTLR4 for Verilog parsing in Python

cxxrtl-vpi

An IEEE-1364 VPI interface for CXXRTL (the Yosys C++ simulation backend), so cocotb can drive CXXRTL models.

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

sv2svg

SystemVerilog to SVG using Schemdraw (left-to-right logic diagrams)

socx-cli

Unified command-line tool for EDA development teams to streamline common tasks and tools, and unify them under a single configurable CLI menu to increase accessibility and transparency of tools and scripts in collaborative development environments.

pyslang-dev

SystemVerilog compiler and language services

svinst

Determines the modules declared and instantiated in a SystemVerilog file

pyxhdl

Python Frontend For VHDL And Verilog

svmodule

SystemVerilog & Verilog Module I/O parser and printer

ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog