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Systemverilog Python Packages

Python packages with the GitHub topic systemverilog. Sorted by relevance, with stars and monthly downloads.
SystemRDL
peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

296K 79 64
SystemRDL
peakrdl

Control and status register code generator toolchain

267K 195 41
MikePopoloski
pyslang

SystemVerilog compiler and language services

229K 1K 224
olofk
edalize

An abstraction library for interfacing EDA tools

161K 770 226
SystemRDL
peakrdl-cli

Control and status register code generator toolchain

65K 195 41
tsfpga
tsfpga

A flexible and scalable development platform for modern FPGA projects.

6K 43 8
Nic30
hdlconvertorast

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

2K 41 12
dau-dev
verilator

Python/PyPI wrapper for Verilator

2K 7 1
sagikimhi
socx-cli

Unified command-line tool for EDA development teams to streamline common tasks and tools, and unify them under a single configurable CLI menu to increase accessibility and transparency of tools and scripts in collaborative development environments.

2K 0 1
davidel
pyxhdl

Python Frontend For VHDL And Verilog

2K 27 2
cristian-mattarei
cosa

CoreIR Symbolic Analyzer

2K 75 18
mtdsousa
antlr4-verilog

Generated files from ANTLR4 for Verilog parsing in Python

1K 12 0
pymtl
pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

1K 453 57
Nic30
hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

1K 225 30
sgherbst
svinst

Determines the modules declared and instantiated in a SystemVerilog file

1K 51 6
SimplHDL
simplhdl

A framework for simulating and implementing HDL designs

1K 8 3
cclienti
svmodule

SystemVerilog & Verilog Module I/O parser and printer

1K 26 4
fundou1081
sv-trace

SystemVerilog static analysis library for RTL tracing, verification, and code quality

755 0 0
Nic30
hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

737 325 78
SymbiFlow
sphinx-verilog-domain

Verilog Domain for Sphinx

658 27 7
ErikMeinders
sv2svg

SystemVerilog (.sv) to SVG visualizer using Schemdraw logic gates.

590 4 0
oddball
ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

553 65 21
MikePopoloski
pyslang-dev

SystemVerilog compiler and language services

535 1K 224
sgherbst
svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

511 51 11
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