Rtl Python Packages

siliconcompiler

Modular hardware build system

pyrtl

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.

hdl-registers

An open-source HDL register code generator fast enough to run in real time.

neosyn-fpga-mcp

MCP server for FPGA hardware design in C⏚ - agents write a C-like HDL; the server compiles, checks, generates Verilog and synth-checks against the real toolchain.

wave-mcp

Open-source, license-free MCP server for RTL waveform debug: reads FST waveforms (VCD/FSDB auto-convert) plus a SystemVerilog netlist, with 34 tools covering driver analysis, value/X tracing, pass-fail waveform diff, a browser wave viewer the agent drives, and pre-simulation static analysis.

arabic-lint

Find Arabic text corrupted by reshape+bidi before it was stored. Zero dependencies, CI-ready.

django-tabular-permissions

Display Django permissions in a HTML table that is translatable and easily customized.

zkf

Zubax Kulibin Float (ZKF) -- an efficient floating-point engine for controls & embedded following IEEE 754 sans NaN and subnormals

tsfpga

A flexible and scalable development platform for modern FPGA projects.

booley-rtl

The open-source agentic RTL IDE

iwork-studio

The safe way to let AI edit your Numbers, Keynote and Pages files. Designed decks from your data and brand, checked as rendered; Arabic/RTL-ready; every change backed up, verified and undoable. MCP server + Python library + agent skill for Claude and any MCP client.

openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

digsim-logic-simulator

An interactive digital logic simulator with verilog support (Yosys)

django-unfold-farsi

Drop-in RTL and Persian (Farsi) localization with Vazirmatn typography for django-unfold admin.

smooth-reading

Open-source, framework-friendly guided fixation reading for Web, iOS, Android, Flutter, Rust and Python

cg-agent-kit

MCP server for FPGA hardware design in C⏚ - agents write a C-like HDL; the server compiles, checks, generates Verilog and synth-checks against the real toolchain.

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

tervatrix-rtl

Correct right-to-left text for Hebrew and Arabic in Python. On PyPI as tervatrix-rtl. MIT.

sahifa

Python client for Sahifa: Arabic-ready HTML to PDF and screenshots, rendered in Saudi Arabia (no reshaper, no bidi, no fonts to install)

traceweave-mcp

Open-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM source, hierarchy, and connectivity to trace failures to root cause.

rtl-tty

Fix Persian/Arabic/Hebrew text in terminal AI tools like Claude Code (PTY proxy using the terminal's own SCP escape)

sphinx-verilog-domain

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

hwtlib

hardware library for hwt (= ipcore repo)