Rtl Python Packages

siliconcompiler

Modular hardware build system

tsfpga

A flexible and scalable development platform for modern FPGA projects.

pyrtl

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.

hdl-registers

An open-source HDL register code generator fast enough to run in real time.

django-tabular-permissions

Display Django permissions in a HTML table that is translatable and easily customized.

pyautoclick

Hold-to-click and auto-click with global hotkeys, multi-language UI.

pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

hwtlib

hardware library for hwt (= ipcore repo)

digsim-logic-simulator

An interactive digital logic simulator with verilog support (Yosys)

sphinx-verilog-domain

Verilog Domain for Sphinx

sphinxcontrib-hdl-diagrams

Generate diagrams from HDL in Sphinx.

sphinxcontrib-verilog-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

sdrterm

Terminal-based tools for (mostly SDR-originated) signal analysis

ariths-gen

Arithmetic circuits generator to Verilog, BLIF, C etc.

sphinx-minoo-theme

A simple Sphinx theme with right-to-left languages support.

openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

django-unfold-admin

RTL Unfold Django Admin Panel Theme

pueda

Collection of python for micro-Electronic Design Automation

py-hcl

A Hardware Construct Language

markdown-autodirection

Extension for markdown package to set paragraph direction to `auto`