Risc V Python Packages

sherpa-onnx-core

Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages

sherpa-onnx

Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages

sherpa-onnx-bin

Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages

riscemu

RISC-V emulator in python

coreblocks

RISC-V out-of-order core for education and research purposes

bronzebeard

Minimal assembler and ecosystem for bare-metal RISC-V development

tinyfive

TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples

labwired

Deterministic firmware simulator for microcontrollers with hardware-validated parity. Labwired.com

wfloat-sherpa-onnx

Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages

river-core

RiVer Core is an open source Python based RISC-V Core Verification framework.

riscv-assembler

RISC-V Assembly code assembler package for Python.

loop-timing-witness

FPGA control-loop event witness software and RTL simulation for PolarFire SoC; physical board qualification pending.

ruapu

Detect CPU features with single-file

chipleap

From an AI workload or your own RTL to a chip GDS on IHP SG13G2, checked with DRC and LVS: architecture exploration with every decision explained, X-HEEP SoC or AXI4 IP generation, and an open digital flow from lint and formal to DFT, pad ring and signoff. MCP server.

tree-sitter-riscv

🌳 RISC-V assembly grammar for tree-sitter.

seal5

Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization

haas-python-max7219

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haas-python-lcd1602

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haas-python-ssd1306

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atomik-core

Delta-state algebra — O(1) state reconstruction, 99% bandwidth reduction, formally proven with 92 Lean4 theorems. pip install atomik-core | C99 header | FPGA hardware (69.7 Gops/s)

haas-python-sh1106

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fast-audio-resampler

Audio resampling focused on x86/x86_64, AArch64 ARM, and RISC-V CPUs

haas-python-hcsr04

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haas-python-neo-pixel-matrix

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