Physical Design Python Packages

rta-constraint-intelligence

Ṛta — deterministic SDC constraint intelligence for block-level VLSI design. Validate, generate, lint, convert and analyze timing constraints before STA, with clock intelligence, coverage, conflict detection, readiness scoring, diff, MMC and CI gates. 1,200+ tests, 119 rules, fully offline — no LLM.

physdes-py

🧱 Physical Design Python Code

mnt-bench

MNT Bench - An MNT tool for Benchmarking FCN circuits