Netlist Python Packages

najaeda

Netlist API (and more) for EDA flow development

spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

eda-netlist-parser

A pure-Python parser for SPICE, Spectre, CDL, and DSPF netlist files — extracts subcircuit, port, device, and parasitic data for EDA automation and library characterization workflows.

circuitgraph

Tools for working with circuits as graphs in python

sim-plugin-ltspice

LTspice driver for sim — bundled .asc/.net/.raw/.log library + driver in one wheel.

circuitsim

Perform gate-level simulations from python

pcbdl

PCB Design Language: A programming way to design schematics.