Netlist Python Packages

najaeda

Netlist API (and more) for EDA flow development

naja-schematic

Portable netlist schematic viewer for the naja data model

naja-scope

MCP server for AI agents to explore SystemVerilog/Verilog netlists: trace connectivity, walk hierarchy, jump to source - without pasting RTL into context. Built on najaeda.

perfboard-studio

Design circuits on perfboard the way you would on a PCB — netlist-driven placement and routing, perfboard-specific DRC, LVS, and a soldering guide with measurement checkpoints.

spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

akcli-kicad

AI-native schematic design agent, purpose-built for KiCad (zero-dependency pure-stdlib Python CLI): author and edit .kicad_sch from JSON op-lists with net-diff safety rails, run ERC/design/intent/BOM checks, simulate on KiCad's bundled ngspice, source real parts and fetch datasheets, and import Altium .SchDoc/.SchLib/.PcbDoc read-only into KiCad

helix-grounding

Catch the numbers an AI made up, without asking another AI

kicad-netspec

Verify PCB connectivity against declared engineering intent, using KiCad as the oracle.

schematizer

Turn a generic, hierarchical netlist (JSON) into a KiCad schematic.

circuitgraph

Tools for working with circuits as graphs in python

eda-netlist-parser

A pure-Python parser for SPICE, Spectre, CDL, and DSPF netlist files — extracts subcircuit, port, device, and parasitic data for EDA automation and library characterization workflows.

perfstudio

Design circuits on perfboard the way you would on a PCB — netlist-driven placement and routing, perfboard-specific DRC, LVS, and a soldering guide with measurement checkpoints.

pcbdl

PCB Design Language: A programming way to design schematics.

sim-plugin-ltspice

Use AI coding agents with LTspice via sim-cli: run circuits, inspect waveforms/logs, and produce replayable simulation artifacts.

circuitsim

Perform gate-level simulations from python