icarus-verilog
An abstraction library for interfacing EDA tools
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
A generic verification interface to Verilog simulators using TCP sockets
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
🪀 Tool to play with HDL (inspired by EdaPlayground)
