Hardware Verification Python Packages

booley-rtl

The open-source agentic RTL IDE

cosa

CoreIR Symbolic Analyzer

traceweave-mcp

Open-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM source, hierarchy, and connectivity to trace failures to root cause.

socx-cli

Unified command-line tool for EDA development teams to streamline common tasks and tools, and unify them under a single configurable CLI menu to increase accessibility and transparency of tools and scripts in collaborative development environments.

toroid

An agent that reads a spec and RTL, proposes formal properties, runs a model checker, and iterates on counterexamples — automating the hardware verification engineer's loop.

btor2-opt

Btor2 parser, circuit mitter, and code optimizer

cxxrtl-vpi

An IEEE-1364 VPI interface for CXXRTL (the Yosys C++ simulation backend), so cocotb can drive CXXRTL models.

sc-cxxrtl

A CXXRTL cocotb simulator for SiliconCompiler — installed, not patched in. Built on cxxrtl-vpi.

rvgen

Pure-Python RISC-V instruction generator with built-in functional coverage, auto-regression, and CI-ready dashboards.

verlpy

VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (RL). It provides a generic Gym environment implementation for building cocotb-based testbenches for verifying any hardware design.