Hardware Design Python Packages

neosyn-fpga-mcp

MCP server for FPGA hardware design in C⏚ - agents write a C-like HDL; the server compiles, checks, generates Verilog and synth-checks against the real toolchain.

booley-rtl

The open-source agentic RTL IDE

cg-agent-kit

MCP server for FPGA hardware design in C⏚ - agents write a C-like HDL; the server compiles, checks, generates Verilog and synth-checks against the real toolchain.

np2hw

NumPy → streaming ISP hardware (Verilog) compiler

simuhw

A behavioral hardware simulator provided as a Python module

hw-codesign

Agentic hardware co-design: brief to KiCad, firmware, 3D review, and explicit fabrication blockers.