Hardware Description Language Python Packages

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

peakrdl

Control and status register code generator toolchain

peakrdl-cli

Control and status register code generator toolchain

neosyn-fpga-mcp

MCP server for FPGA hardware design in C⏚ - agents write a C-like HDL; the server compiles, checks, generates Verilog and synth-checks against the real toolchain.

cg-agent-kit

MCP server for FPGA hardware design in C⏚ - agents write a C-like HDL; the server compiles, checks, generates Verilog and synth-checks against the real toolchain.

pyshdl

A minimalist HDL built entirely from logic gates for education and experimentation. Compiles circuits to C so that they can run anywhere

pycircuit-hisi

Python-first hardware construction toolkit with MLIR compilation, C++ simulation, and Verilog generation.

peakrdl-check

Semantic compatibility analysis and configurable quality gates for SystemRDL specifications. Detects firmware-breaking register changes, produces CI reports and provides scalable exploration of large register maps.