Fpga Python Packages

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

peakrdl-ipxact

Import and export IP-XACT XML register models

peakrdl-html

Generate address space documentation HTML from compiled SystemRDL input

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl

Control and status register code generator toolchain

siliconcompiler

Modular hardware build system

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

edalize

An abstraction library for interfacing EDA tools

peakrdl-uvm

Generate UVM register model from compiled SystemRDL input

peakrdl-cli

Control and status register code generator toolchain

fxpmath

A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.

amaranth

A modern hardware definition language and toolchain based on Python

yowasp-yosys

Unofficial Yosys WebAssembly packages

vunit-hdl

VUnit is a unit testing framework for VHDL/SystemVerilog

najaeda

Netlist API (and more) for EDA flow development

apollo-fpga

microcontroller-based FPGA / JTAG programmer

blackiceprog

Multiplatform script to upload bitstream to BlackIce FPGAs from mystorm

qonnx

QONNX: Arbitrary-Precision Quantized Neural Networks in ONNX

dace

DaCe - Data Centric Parallel Programming

apio

:seedling: Open source ecosystem for open FPGA boards

litex

Build your hardware, easily!

brevitas

Brevitas: neural network quantization in PyTorch

hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

hgq

Legacy High Granularity Quantizarion 1 - Please use HGQ2 instead (https://github.com/calad0i/HGQ)