Fpga Python Packages

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

peakrdl-ipxact

Import and export IP-XACT XML register models

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl

Control and status register code generator toolchain

peakrdl-html

Generate address space documentation HTML from compiled SystemRDL input

edalize

An abstraction library for interfacing EDA tools

peakrdl-uvm

Generate UVM register model from compiled SystemRDL input

fxpmath

A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.

peakrdl-cli

Control and status register code generator toolchain

siliconcompiler

Modular hardware build system

qonnx

QONNX: Arbitrary-Precision Quantized Neural Networks in ONNX

amaranth

A modern hardware definition language and toolchain based on Python

specsmith

AEE governance CLI for AI-assisted dev — WI lifecycle (specsmith wi), preflight gates, multi-agent dispatch, requirements<->test traceability, ESDB, MCP server, compliance, 64 project types, 136 skills, and 1607 tests.

najaeda

Netlist API (and more) for EDA flow development

dace

DaCe - Data Centric Parallel Programming

yowasp-yosys

Unofficial Yosys WebAssembly packages

vunit-hdl

VUnit is a unit testing framework for VHDL/SystemVerilog

apollo-fpga

microcontroller-based FPGA / JTAG programmer

brevitas

Brevitas: neural network quantization in PyTorch

apio

:seedling: Open source ecosystem for open FPGA boards

blackiceprog

Multiplatform script to upload bitstream to BlackIce FPGAs from mystorm

litex

Build your hardware, easily!

sc-neurocore

Universal Stochastic Computing Framework for Neuromorphic Hardware — Rust SIMD engine, Python simulation, Verilog RTL, HDC/VSA, SCPN integration