Asic Python Packages

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

peakrdl-ipxact

Import and export IP-XACT XML register models

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl

Control and status register code generator toolchain

peakrdl-html

Generate address space documentation HTML from compiled SystemRDL input

peakrdl-uvm

Generate UVM register model from compiled SystemRDL input

peakrdl-cli

Control and status register code generator toolchain

siliconcompiler

Modular hardware build system

najaeda

Netlist API (and more) for EDA flow development

vunit-hdl

VUnit is a unit testing framework for VHDL/SystemVerilog

librelane

ASIC implementation flow infrastructure, successor to OpenLane

fabulous-bit-gen

Bitstream generation for FABulous FPGAs

tsfpga

A flexible and scalable development platform for modern FPGA projects.

simplhdl

Simulation and implementation flow for hardware description languages

skillbridge

A seamless python to Cadence Virtuoso Skill interface

asic-mcp

MCP server for Australian Securities and Investments Commission registers. Plain-English access to financial advisers, AFS licensees, credit licensees, banned and disqualified persons and organisations, and registered liquidators via data.gov.au.

hdl-registers

An open-source HDL register code generator fast enough to run in real time.

fabulous-fpga

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

corsair

Control and Status Register map generator for HDL projects

mera

An heterogeneous deep learning compiler framework.

whatsminer

Unofficial python API for MicroBT Whatsminer ASICs

asic-rag-chimera

GPU simulation of a SHA-256 hash engine inspired by Bitcoin mining ASICs, wired into a RAG pipeline. Pure software; no real ASIC hardware required.

ralbot-uvm

Generate UVM register model from compiled SystemRDL input

libsv

An open source, parameterized SystemVerilog digital hardware IP library