Asic Python Packages

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

peakrdl-ipxact

Import and export IP-XACT XML register models

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl

Control and status register code generator toolchain

peakrdl-html

Generate address space documentation HTML from compiled SystemRDL input

peakrdl-uvm

Generate UVM register model from compiled SystemRDL input

siliconcompiler

Modular hardware build system

peakrdl-cli

Control and status register code generator toolchain

librelane

ASIC implementation flow infrastructure, successor to OpenLane

najaeda

Structural Netlist API (and more) for EDA post synthesis flow development

vunit-hdl

VUnit is a unit testing framework for VHDL/SystemVerilog

asic-mcp

Query the Australian Securities and Investments Commission registers in plain English from Claude or any MCP client. Financial advisers, AFS / credit licensees, banned persons & orgs, liquidators.

skillbridge

A seamless python to Cadence Virtuoso Skill interface

fabulous-bit-gen

Bitstream generation for FABulous FPGAs

tsfpga

A flexible and scalable development platform for modern FPGA projects.

hdl-registers

An open-source HDL register code generator fast enough to run in real time.

simplhdl

A framework for simulating and implementing HDL designs

corsair

Control and Status Register map generator for FPGA/ASIC projects

fabulous-fpga

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

asic-rag-chimera

Hardware-Accelerated Cryptographic RAG System — GPU simulation of SHA-256 hash engine with AES-256-GCM encryption and Merkle tree integrity. NOT real ASIC hardware.

mera

An heterogeneous deep learning compiler framework.

whatsminer

Unofficial python api for MicroBT Whatsminer ASICs

libsv

An open source, parameterized SystemVerilog digital hardware IP library

ralbot-uvm

Generate UVM register model from compiled SystemRDL input