Asic Python Packages

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

peakrdl-ipxact

Import and export IP-XACT XML register models

peakrdl-html

Generate address space documentation HTML from compiled SystemRDL input

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl

Control and status register code generator toolchain

siliconcompiler

Modular hardware build system

peakrdl-uvm

Generate UVM register model from compiled SystemRDL input

peakrdl-cli

Control and status register code generator toolchain

vunit-hdl

VUnit is a unit testing framework for VHDL/SystemVerilog

najaeda

Netlist API (and more) for EDA flow development

librelane

ASIC implementation flow infrastructure, successor to OpenLane

hdl-registers

An open-source HDL register code generator fast enough to run in real time.

skillbridge

A seamless python to Cadence Virtuoso Skill interface

kepler-formal

Digital Design Equivalence Checking

tsfpga

A flexible and scalable development platform for modern FPGA projects.

booley-rtl

The open-source agentic RTL IDE

asic-mcp

Query the Australian Securities and Investments Commission registers in plain English from Claude or any MCP client. Financial advisers, AFS / credit licensees, banned persons & orgs, liquidators.

simplhdl

Simulation and implementation flow for hardware description languages

fabulous-fpga

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

corsair

Control and Status Register map generator for HDL projects

peakrdl-check

Semantic compatibility analysis and configurable quality gates for SystemRDL specifications. Detects firmware-breaking register changes, produces CI reports and provides scalable exploration of large register maps.

chipleap

From an AI workload or your own RTL to a chip GDS on IHP SG13G2, checked with DRC and LVS: architecture exploration with every decision explained, X-HEEP SoC or AXI4 IP generation, and an open digital flow from lint and formal to DFT, pad ring and signoff. MCP server.

whatsminer

Unofficial python api for MicroBT Whatsminer ASICs

asic-rag-chimera

Hardware-Accelerated Cryptographic RAG System — GPU simulation of SHA-256 hash engine with AES-256-GCM encryption and Merkle tree integrity. NOT real ASIC hardware.